1. Field of the Invention
The present invention relates generally to reducing dynamic power consumption in digital system designs.
2. Background
Clock signals are used to define a time reference for the movement of data within a synchronous digital system. A clock distribution network distributes clock signals from a common point in the system to elements in the system that require clock signals. Oftentimes, a significant amount of power can be wasted in clock transitions in these elements when an output of an element is not needed in the digital system. More specifically, a large amount of current is drawn from a system's power grid as transistors that control the clock signal switch states. These high current demands cause noise in the system due to voltage drops and inherent system inductance (L di/dt). Consequently, this noise can cause missed timings if the clock signal voltage is too low, or system failure if the clock signal voltage is too high.
A large amount of dynamic power is consumed when the digital system powers ON and OFF. More specifically, as the system is activated, the clock distribution network activates all of the system's clock signals, thus drawing a large amount of current at one time from the system's power grid. The instantaneous current drawn from the system's power grid due to switching ON of the clock distribution network may be referred to as a “di/dt” effect, which represents a change in current in the power grid over time. Conversely, as the clock distribution network de-activates, all of the system's clock signals shutdown, drawing a large amount of current as switching transistors in the clock signals transition from an active state to an idle state (e.g., transition from ‘1’ to ‘0’). As the number of devices in the system grows, thus increasing the number of clock signals in the clock distribution network to control these additional devices, the susceptibility of missed timings and system failure becomes greater due to an increase in dynamic power when the system powers ON and OFF.
Accordingly, what is needed is a method to control the effects of di/dt as the clock distribution network is activated and de-activated and to shut off clock signals in the clock distribution network when idle, thus reducing dynamic power consumption.